In older x86 hardware, typically pre-64 bit, control of the CPU cache was done by using settings in MTRR or Memory Type Range Registers. These allowed sections of memory to be cached in different ways. Memory could be set uncacheable, write-back, or write-combining. The feature was most commonly used with graphics cards to control how the CPU would cache the memory on the card when mapped into the address space of the CPU. The number of ranges that can be controlled is limited.
Newer x86-64 machines use PAT, or Page Attribute Table, to control how memory is cached. Unlike the limited ranges of memory that can be controlled with MTRRs, PAT allows every memory page (4M on an x64 CPU) to be configured with a specific caching method.
I have noticed on some systems that the NVIDIA driver for linux, as it is setting up the caches, will comment that PAT was unavailable and fall back to MTRR. (Such as Xen 3 installations)
You can check your CPU to see if it supports these features with the following unix command.
egrep --color '(mtrr|pat)' /proc/cpuinfo